HyperX Architecture Training at Coherent Logix!

Coherent Logix has just completed another successful round of customer training in our Austin, TX office. Bryan Schleck, our lead trainer, is featured in the  above photo actively engaging the audience.

Interested in learning more about programming on HyperXTM processors? Email clxinfo@coherentlogix.com!

Training Overview
This training class is intended for engineers who desire a more in-depth understanding of the HyperX architecture and who are preparing to develop software designs using HyperX technology.

Objectives

At the end of this class the student should be able to:

  • Use the HyperX Integrated Development Environment (hxISDE)tool suite
  • Understand the processor instruction set, communications fabric, and overall architecture
  • Design a scalable parallel system and map the design onto the HyperX processor
  • Create a verification testbench on the HyperX processor
  • Use the hxISDE tools to analyze overall system performance such as throughput, latency, power consumption, etc.

Audience Profile
Algorithm developers, software engineers, signal processing engineers, system architects.

Prerequisites
Some programming experience using the ANSI C language.

Class Outline

This class consists of:

  • An overview of the major components of the HyperX architecture
  • An overview of the key elements in the software development environment
  • A detailed description of the FAST* design process that takes an application from analysis through implementation for the HyperX parallel processing architecture (*Functional Analysis, Architectural Constraints, System Design, Transformation to Hardware)
  • An introductory example that takes the user through the steps to create, build, and simulate a design from scratch
    • Involves the basic usage and navigation of the hxISDE tool suite
    • Illustrates how to work with software code using the Managed Build Environment (MBE)
    • Shows how to build a project and map a design onto the HyperX processor
    • Introduces the concepts of multi-processing, parallelization and communication APIs
  • A more complex example that takes an algorithm through the FAST design process
    • Takes the user from a simple design all the way to a scalable algorithm design
    • Shows how to set up a testbench for design verification
    • Introduces the user to the details of how to create a design using reusable components (“cells”)
    • Shows how to use the tools to analyze the overall design performance on hardware

Tools Used

  • HyperX Integrated System Development Environment
  • Hardware Evaluation Board

LET’S CREATE SOMETHING TOGETHER

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