Low Power Processing, Redefined.
The HyperX™ computing platform offers unprecedented power efficiency coupled with high performance, programming ease, and scalability to support single chip handheld devices through multi-chip rack mounted systems.
The HyperX processor’s unique capability is realized by interconnecting energy efficient processing cores with an instant-on and bandwidth-on-demand network fabric, while at the same time offering a seamless hardware programming model across cores and chip boundaries.
The HyperX hx3100 is composed of an array of 100 processing elements (PEs), each of which is a fully capable 500MHz DSP/GPP processor core with 4 kB program memory. PEs support 8-bit, 16-bit, extended precision integer, and 32-bit single-precision floating-point. The hx3100 is capable of 50,000 MIPS (50 GMACs) performance or 25 GFLOPS, with total core power consumption ranging from 25 mW to 2.5 W (typical, algorithm dependent).
Interconnected within the PE matrix is a memory and communication network of 121 data memory routers (DMRs), each with 8 kB data memory, and 8 DMAs to facilitate autonomous data movement across the chip. Programmable I/O routers surround the PE-DMR fabric, supporting greater than 104 Gbps of data throughput via a high-speed memory (DDR2) interface and general purpose LVDS/CMOS I/O channels. Custom packaging is also available to support up to 168 Gbps of I/O bandwidth in customer defined footprints.